In modern high-speed and high-density PCB design, stack-up architecture is a foundational factor that directly determines signal integrity (SI), power integrity (PI), and electromagnetic compatibility (EMC).
As operating frequencies increase and edge rates become faster, the physical arrangement of signal, power, and ground layers becomes just as critical as schematic design.
A well-structured stack-up not only defines controlled impedance and stable return paths for high-speed signals, but also reduces loop areas, suppresses radiation, and improves noise immunity across the entire system.
To achieve these objectives, PCB stack-up design is generally guided by a set of fundamental principles.
The most important requirement is that every high-speed signal layer must have an adjacent reference plane—typically a solid ground or power layer—to ensure a continuous and low-inductance return path.
Closely spaced power and ground planes generate sufficient interplane capacitance, which stabilizes voltage rails and suppresses switching noise.
Designers apply different stack-up configurations for two-layer, four-layer, six-layer, and eight-layer boards based on these core principles.
They optimize each configuration according to circuit complexity, component density, and performance requirements.
In general, stack-up design must adhere to two main rules:
1. Each signal layer must have an adjacent reference layer (power or ground layer);
2. Adjacent main power and ground layers must maintain a minimum spacing to provide sufficient coupling capacitance;
The following examples illustrate stack-ups ranging from two-layer to eight-layer boards:
Stack-up for Single-Sided and Double-Sided PCBs
For two-layer boards, due to the small number of layers, stack-up issues do not arise. Controlling EMI radiation is primarily addressed through routing and layout considerations;
Electromagnetic compatibility (EMC) issues are becoming increasingly prominent in single-layer and double-layer boards.
The main cause of this phenomenon is the excessive area of signal loops, which not only generates strong electromagnetic radiation but also makes the circuit sensitive to external interference.
Principle: Reducing Signal Loop Area
The simplest way to improve the electromagnetic compatibility of a circuit is to reduce the loop area of critical signals.
Definition of Critical Signals
Critical signals: From an electromagnetic compatibility perspective, critical signals primarily refer to signals that generate strong radiation and signals that are sensitive to external interference.
Signals capable of generating strong radiation are generally periodic signals, such as clock signals or the least significant bits of address signals.
Signals sensitive to interference refer to those with low-level analog signals.
Single- and double-layer boards are typically used in low-frequency analog designs below 10 kHz:
Layout and Routing Guidelines for Single- and Double-Layer Boards
1) Route power lines on the same layer in a radial pattern and minimize the total length of the lines;
2) Route power and ground lines close to each other; route a ground line alongside critical signal lines, keeping it as close to the signal lines as possible.
This creates a smaller loop area, reducing sensitivity to external interference from common-mode radiation.
Layer Stacking for Two- and Four-Layer Boards
Common Stack-Up Schemes
1. SIG-GND (PWR)-PWR (GND)-SIG;
2. GND-SIG (PWR)-SIG (PWR)-GND;
These two stack-up configurations exhibit a common limitation when implemented with the conventional 1.6 mm (62 mil) PCB thickness.
Designers encounter excessively large interlayer spacing, which degrades impedance control, weakens interlayer coupling, and reduces shielding effectiveness.
The increased distance between power and ground planes lowers the intrinsic board capacitance, thereby diminishing the ability of the system to suppress and filter noise efficiently.
Application Characteristics of the First Scheme
The first scheme is typically used when there are many chips on the board.
This scheme achieves good SI performance, but EMI performance is not ideal and must be controlled primarily through routing and other design details.
Key considerations: Place the ground plane on the layer adjacent to the signal layer with the highest signal density to help absorb and suppress radiation; increase the board area to comply with the 20H rule.
Application Characteristics of the Second Scheme
The second approach is typically used when the chip density on the board is sufficiently low and there is sufficient area around the chip (to accommodate the required power copper layer).
In this approach, the outer layers of the PCB are all ground planes, and the two middle layers are signal/power layers.
Power traces on the signal layers should be routed using wide traces.
This ensures low impedance for the power current path and low impedance for the signal microstrip paths, while the outer ground layers also shield the inner signal layers from radiation.
From an EMI control perspective, this is currently the best 4-layer PCB structure available.
Layout Constraints and EMI Optimization Notes
Designers must space the two middle mixed signal/power layers apart and route traces perpendicular to each other to avoid crosstalk.
They should also control the board area appropriately to comply with the 20H rule.
When trace impedance requires control, the design demands very careful placement of traces beneath the power and ground copper planes.
Designers should also interconnect the copper planes on the power and ground layers as much as possible to ensure DC and low-frequency connectivity.
Layer Stacking for 6-Layer Boards
For designs with high chip density and high clock frequencies, a 6-layer board should be considered.
The recommended layer stacking sequence is:
1. SIG-GND-SIG-PWR-GND-SIG;
This stack-up configuration delivers strong signal integrity performance. Designers place signal layers directly adjacent to ground reference layers to maintain stable return paths.
Engineers pair power layers with ground layers to stabilize the power distribution network.
Careful layer pairing and spacing control enable controlled impedance across all routing layers.
Ground planes actively absorb magnetic flux lines, reducing electromagnetic interference throughout the structure.
Furthermore, with complete power and ground planes, it provides a good return path for each signal layer.
2. GND-SIG-GND-PWR-SIG-GND;
This configuration is only suitable for applications with relatively low component density.
It offers all the advantages of the stack-up described above, and the ground planes on the top and bottom layers are more complete, serving as effective shielding layers.
Designers should place the power layer close to the side opposite the main component side.
This placement allows the bottom-layer ground plane to remain more continuous and complete.
Consequently, EMI performance is better than in the first scheme.
Summary: Six-layer board designs should minimize the spacing between the power layer and the ground layer to achieve strong power–ground coupling.
A standard 62 mil board thickness still limits how tightly the main power and ground layers can be placed, even when designers reduce interlayer spacing.
Comparing the first and second schemes, the second option results in significantly higher costs. Therefore, we typically choose the first scheme when stacking layers. During design, follow the 20H rule and the mirrored layer rule.
Stacking for Eight-Layer Boards
Non-Optimal Stack-Up Configuration
Due to poor electromagnetic absorption and high power supply impedance, this is not an optimal stacking method.
Its structure is as follows:
1) Signal 1: Component side, microstrip trace layer
2) Signal 2: Internal microstrip trace layer, with good trace performance (X-direction)
3) Ground
4) Signal 3: Stripline trace layer, with good trace performance (Y-direction)
5) Signal 4: Stripline trace layer
6) Power
7) Signal 5: Internal microstrip trace layer
8) Signal 6: Microstrip trace layer
Improved Stack-Up with Added Reference Planes
This is a variation of the third stacking method.
Adding a reference layer improves EMI performance. It also enables precise control of the characteristic impedance on each signal layer.
1) Signal 1: Component side, microstrip trace layer; good routing layer
2) Ground: Ground layer; good electromagnetic wave absorption capability
3) Signal 2: Stripline routing layer; good routing layer
4) Power: Power supply layer; forms excellent electromagnetic absorption with the ground layer below
5) Ground: Ground layer
6) Signal 3: Stripline routing layer; good routing layer
7) Power: Power supply layer; has high power supply impedance
8) Signal 4: Microstrip routing layer; good routing layer
Optimal Stack-Up Configuration
The use of multiple ground reference planes provides excellent electromagnetic absorption.
1) Signal 1: Component side, microstrip trace layer; good trace layer
2) Ground layer; good electromagnetic wave absorption
3) Signal 2: Stripline trace layer; good trace layer
4) Power: Power supply layer; provides excellent electromagnetic absorption in conjunction with the ground layer below
5) Ground: Ground layer
6) Signal 3: Stripline trace layer; good trace layer
7) Ground: Ground layer; good electromagnetic wave absorption capability
8) Signal 4: Microstrip trace layer; good trace layer
Engineers determine the appropriate number of PCB layers and select a suitable stack-up structure based on multiple design constraints.
These constraints include the number of signal networks on the board, component density, pin density, signal frequency, and overall board size.
Engineers should evaluate all of these factors in a comprehensive manner.
When a design includes a large number of signal networks, along with high component density, high pin density, and high signal frequencies, engineers should adopt a multilayer board design whenever possible.
To achieve good EMI performance, it is best to ensure that each signal layer has its own reference layer.
Conlusion
In summary, PCB stack-up design is a critical engineering discipline that directly governs the electrical performance, noise behavior, and overall reliability of modern electronic systems.
Designers maintain a consistent set of core principles across all PCB layer counts, ranging from simple two-layer boards to complex eight-layer structures.
High-speed signals require a tightly coupled return path that runs through an adjacent reference plane, ensuring stable current flow and controlled electromagnetic behavior.
Engineers carefully engineer power–ground pairing to achieve low impedance distribution networks and effective decoupling performance.
As PCB layer complexity increases, stack-up optimization evolves beyond basic routing considerations.
It becomes an integrated electromagnetic design challenge that requires simultaneous balancing of signal integrity, power distribution, and EMI suppression.
Proper use of ground planes for shielding, controlled interlayer spacing for impedance stability, and strategic layer mirroring for return-path continuity all contribute to improved system performance.
Ultimately, there is no universal “best” stack-up; the optimal solution depends on application requirements such as signal frequency, component density, board size, and manufacturing constraints.
However, by consistently applying the principles of short return paths, strong reference coupling, and minimized loop area, designers can systematically achieve robust, low-noise, and high-performance PCB layouts across a wide range of applications.
