As the data rates of high-speed interconnect links continue to increase, the signal integrity of printed circuit boards (PCBs)—which serve as the medium for signal transmission—is having an increasingly significant impact on system performance.
The widespread commercialization of PCIe 4.0 and PCIe 5.0 server products has increased the demand for high-speed PCBs.
As technologies such as PCIe 6.0 continue to develop, controlling PCB insertion loss has become a critical measure in the high-speed PCB manufacturing process.
The factors influencing signal loss primarily include design, materials, conductor resistance, dielectric thickness, conductor roughness, conductor thickness, and trace width.
Design and substrate materials cause the dominant losses, followed by the influence of manufacturing processes;
Figure 1 shows the specific proportions of these influences.
This paper focuses on researching the impact of high-speed PCB manufacturing processes on signal loss.
Test Section
For this study, the experiment used reverse-treated copper foil (RTF) with varying surface roughness.
The experiment tested three different browning solutions.
It also tested various circuit surface roughening methods and solder mask inks with different dielectric loss (Df) values.
The experiment included both back-drilled and non-back-drilled conditions as factors influencing signal loss.
Test Layouts and Stackup Design
Using the Delta-L 4.0 standard test module (as shown in Figure 2), the experiment designed 5-inch (127 mm) and 10-inch (254 mm) dual-line structures.
These structures meet the loss testing requirements for high-frequency signals (1–40 GHz).
The module includes calibration and test sections, which eliminate additional loss and interference from fixtures and connection points.
The prototype board is a 16-layer rigid PCB with a thickness of 2.3 mm ± 10%.
It features a symmetrical stack-up structure constructed using ultra-low-loss high-speed laminates, as shown in Figure 3.
Test Materials and Equipment
(1) Board Materials: Ultra-low-loss high-speed board materials; copper foil types RTF1, RTF2, RTF3, RTF4, and RTF5.
(2) Browning Solutions: A, B, and C.
(3) Solder Mask Inks: Conventional Df ink D, low Df inks E
and F.
(4) Roughness Testing Instrument: 3D laser microscope.
(5) Loss testing instrument: Vector network analyzer.
Test Protocol
This protocol uses Delta-L 4.0 as the module testing method.
It employs the controlled variable method to investigate the effect of different RTF copper foils on insertion loss.
The study examines various combinations of browning treatments, outer layer pretreatments, and solder mask pretreatments.
It also tests different solder mask ink types, back-drilling processes, and numbers of reflow cycles.
After the finished test boards pass continuity testing, a vector network analyzer measures insertion loss.
Each test condition repeats three times, and the process calculates the average as the final result to ensure data reliability.
Test Plan Design and Evaluation Factors
Table 1 presents the test plan, and Table 2 lists the specific parameter values for each factor.
| Variable Type | Test Item | Number of Factors | Specific Factors |
|---|---|---|---|
| Material Variables | RTF Copper Foil | 5 | RTF1, RTF2, RTF3, RTF4, RTF5 |
| Material Variables | Solder Mask Ink | 3 | Standard D Ink A, Low D Ink E, Low D Ink F |
| Material Variables | Brown Oxide Treatment | 3 | Brown Oxide A, Brown Oxide B, Brown Oxide C |
| Process Variables | Outer Layer Pre-treatment & Solder Mask Pre-treatment Combination | 4 | Volcanic Ash + Volcanic Ash; Medium Roughening + Volcanic Ash; Volcanic Ash + Ultra Roughening; Medium Roughening + Ultra Roughening |
| Process Variables | Back Drilling | 2 | With Back Drilling; Without Back Drilling |
| Process Variables | Reflow Soldering | 3 | 1 Reflow Cycle; 3 Reflow Cycles; 5 Reflow Cycles |
Tab 1: Insertion Loss Test Plan Design
Material Properties and Process Parameters
| Item | Type | Key Parameters | Remarks |
|---|---|---|---|
| Substrate | Ultra-low loss substrate | Dk / Df (10 GHz): 3.25 / 0.0040 | / |
| Copper Foil | RTF1 ~ RTF5 | RTF1–RTF5 Rz values respectively: 6.36, 5.53, 4.69, 2.36, 0.60 μm | Supplier provides copper foil roughness as Rz (linear data); this paper mainly uses surface data Sz to represent roughness |
| Solder Mask Ink | Standard Df ink D; Low Df solder mask ink E/F | Ink D: Dk / Df (10 GHz): 3.25 / 0.0040Ink E: Dk / Df (10 GHz): 3.15 / 0.0013Ink F: Dk / Df (10 GHz): 3.17 / 0.0016 | — |
| Key Parameter: Micro-etch Amount | Inner layer pre-treatment; Brown oxide A, B, C; Volcanic ash; Medium roughening; Ultra roughening | Inner layer pre-treatment: 0.40–1.20 μmBrown oxide A: 0.18–0.27 μmBrown oxide B/C: 1.00–1.60 μmVolcanic ash: no micro-etchMedium roughening: 0.60–1.40 μmUltra roughening: 0.80–1.40 μm | Inner layer: inner layer pre-treatment, brown oxide A/B/COuter layer: volcanic ash, medium roughening, ultra roughening |
| Back Drilling | Back drill stub | Back drill stub control: 0–12 mil | — |
| Reflow Soldering | Lead-free reflow soldering | Lead-free reflow conditions: (260±5)°C for 20 s; >217°C for 120–150 s | — |
Tab 2: Specific Parameter Values Corresponding to Each Factor
Process Flow
The process flow is as follows:
Inner layer pretreatment → Inner layer etching → Browning → Laminating → Drilling → Plasma treatment → Outer layer electroless copper plating → Outer layer electroplating → Outer layer pretreatment → Outer layer etching → Solder mask pretreatment → Solder mask/marking → Back drilling → Gold plating → Board milling → Final cleaning → Continuity testing → Dielectric loss testing.
Results and Discussion
Effect of Browning Treatment on Signal Loss for Different RTF Copper Foils
Samples were taken from the copper foil after passing through different process stages (RTF copper foil → inner layer pretreatment → browning A/B/C) and subjected to scanning electron microscopy (SEM) analysis.
The observed morphologies are shown in Table 3.
After browning, changes in the morphology of the copper foil were observed.
A 3D laser microscope was used to measure the surface area ratio (Sdr) and the peak-to-valley height difference (Sz) of different RTF copper foils at each process stage, and insertion loss tests were conducted.
The results are as follows:
1. Morphological Changes After Browning
The browning process has a significant effect on the morphology of copper foil.
After Browning A treatment, only a shallow honeycomb-like structure appeared on the surface of the copper foil, with minimal morphological changes;
Browning B and Browning C treatments created distinct honeycomb-like pitting on the copper foil surface.
Browning C produced the greatest pitting depth and the most pronounced honeycomb structure.
These results align with the micro-etching control range of the browning solution (Browning A < Browning B = Browning C).
2. Overall Roughness of Copper Foil
The corrosiveness of the browning solution primarily affects the degree of surface undulation of the copper foil.
The initial state of the raw copper foil determines the height of the surface peaks and valleys.
Together, these two factors determine the overall roughness characteristics of the copper foil.
The changes in Sdr after treatment of different RTF copper foils are shown in Figure 4, and the changes in Sz are shown in Figure 5. The specific patterns are as follows:
(1) Sdr Variation Pattern
Browning A results in the smallest increase in Sdr (average increase <5%), while Browning B and Browning C result in larger increases in Sdr (average increase >15%), with Browning C showing a slightly higher increase than Browning B.
(2) Patterns of Sz variation
The effect of browning on Sz is relatively small (change rate <10%).
RTF1 has the largest Sz (raw material Sz ≈ 6.5 μm), while RTF5 has the smallest Sz (raw material Sz ≈ 0.6 μm).
After undergoing the same process treatment, the relative order of Sz for each copper foil remains unchanged.
3. Insertion Loss Test Results
Figure 6 shows the variation in signal insertion loss for different RTF copper foils under different browning treatments.
Under the same browning process, signal loss decreases as copper foil roughness decreases, fully matching the trends for Sdr and Sz, showing that copper foil roughness strongly affects signal loss.
For the same type of copper foil: signal loss increases as the corrosiveness of the browning solution increases, specifically manifested as Browning C > Browning B > Browning A.
Stronger corrosiveness of the browning solution increases the Sdr on the copper foil surface.
This increase amplifies signal attenuation caused by the skin effect.
In high-speed PCB manufacturing, selecting low-roughness RTF copper foil, such as RTF4 or RTF5, reduces signal loss in inner-layer circuits.
Pairing it with a low-corrosivity browning solution, such as Browning A, further improves signal integrity.
The Effect of Outer Layer Pretreatment and Solder Mask Pretreatment Combinations on Signal Loss
Outer layer pretreatment and solder mask pretreatment primarily improve adhesion between the circuit lines and the solder mask ink; however, different roughening methods change the surface roughness of the conductors, thereby affecting signal loss.
After coating the outer layer circuit lines with low-Df ink E, the insertion loss was tested as shown in Figure 7.
The results indicate that different pretreatment combinations have a significant effect on signal loss.
Specifically, the “volcanic ash + volcanic ash” combination exhibited the lowest signal loss (1.301 dB/in) (1 in ≈ 25.4 mm), while the “medium roughening + ultra-roughening” combination exhibited the highest signal loss (approximately 1.406 dB/in), with a difference in loss reaching 0.105 dB/in.
Analysis indicates that this is because the particles used in the volcanic ash roughening process are finer, causing less damage to the conductor surface; whereas the particles used in medium and ultra-roughening are coarser, significantly increasing the Sdr and Sz values of the conductor surface, which leads to an enhanced skin effect and increased signal loss.
The Effect of Top-Layer Solder Mask Ink on Signal Loss
As a protective layer on the surface of a PCB, the Df of the solder mask ink directly affects the dielectric loss of signals during transmission.
Testing measured the insertion loss for three solder mask inks with different Df values, all pre-treated on both the top layer and the solder mask using the volcanic ash process, as shown in Figure 8.
The Df of solder mask ink positively correlates with signal loss; lower Df results in lower signal loss.
Analysis shows that as Df decreases, the ink experiences less energy loss under high-frequency electric fields, resulting in weaker signal attenuation.
Therefore, in high-speed PCB manufacturing, selecting solder mask inks with low Df is an effective means of reducing signal loss in outer-layer circuits.
The advantages of low-Df inks are particularly evident in the high-frequency range of 16 GHz and above.
The Effect of Back Drilling on Signal Loss in Signal Vias
When a signal via is not back-drilled, a segment of unconnected metal stub remains.
At high frequencies, this stub generates parasitic capacitance and inductance, leading to signal reflection and loss.
Figure 9 shows the insertion loss measured at four frequency points for two processes: signal vias with back drilling and those without. The results indicate:
(1) Low-frequency Band (4 GHz)
The difference in signal loss between back-drilled and non-back-drilled holes is small, and the parasitic effects of the stub are not significant.
(2) High-frequency Band (8 GHz and above)
Signal loss without back-drilling is significantly higher than with back-drilling, and the difference increases with higher frequencies.
At 16 GHz, signal loss without back-drilling is 0.102 dB/in higher than with back-drilling, representing a difference of 13.5%.
Analysis shows that as frequency increases, the parasitic reactance of the stump increases, leading to more severe signal reflection and attenuation within the stump.
Therefore, for high-speed PCBs operating at frequencies of 8 GHz or higher, the back-drilling process for signal vias is a necessary measure to suppress high-frequency signal loss, effectively improving signal transmission integrity and reliability.
The Effect of Reflow Soldering on Signal Loss
Reflow soldering is a critical process in PCB assembly.
The high-temperature environment may cause changes in the properties of the materials within the PCB (substrate, copper foil, and solder mask), which in turn affects signal loss.
Three types of low-roughness copper foil combined with a Browning A process to fabricate test boards.
Insertion loss variation rates were measured after 1, 3, and 5 reflow cycles, as shown in Figure 10.
The results indicate that reflow soldering has a minimal impact on signal loss; the rate of change in loss for all test boards was within 1%, with no discernible pattern.
Analysis revealed that the ultra-low-loss substrate and low-Df solder mask used in the test exhibit excellent high-temperature stability.
During the reflow process, there were no significant changes in the materials’ Dk, Df, or copper foil roughness, resulting in signal loss remaining essentially stable.
In summary, within the normal range of reflow soldering cycles (1–3 times), reflow soldering does not significantly affect signal loss in high-speed PCBs, and there is no need to worry about the reflow soldering process compromising signal integrity.
Conclusion
This study demonstrates that copper foil and the browning solution are key factors affecting conductor roughness and signal loss.
Specifically, copper foil primarily influences Sz, while the browning solution primarily affects the Sdr amplitude.
Engineers should use RTF4 or RTF5 copper foil with a low-etch browning solution to reduce signal loss.
Among other factors affecting signal loss, back drilling has a significant impact on high frequencies.
Beyond 8 GHz, signal loss without back drilling is notably greater, and the difference becomes more pronounced at higher frequencies.
Engineers should use back drilling to shorten metal stubs and reduce signal loss; they should prioritize the dual-volcanic ash process for outer layers and solder mask pretreatment, and select low-Df solder mask inks to minimize loss.
Reflow soldering has a minimal impact on signal loss and does not require additional control measures.
This paper provides conclusions solely as a reference for optimizing PCB manufacturing processes; engineers must comprehensively evaluate and adjust based on specific operating conditions.
